Conduc Inc

BIPARTISAN INFRASTRUCTURE LAW (BIL) CARBON COMPOSITE HIGH VOLTAGE DIRECT CURRENT CONDUCTOR EXPANSION (CCHCE) THE OBJECTIVE OF THIS PROJECT IS TO BUILD TS CONDUCTOR CORP’S (THE RECIPIENT) DEDICATED MANUFACTURING LINE FOR HIGH VOLTAGE DIRECT CURRENT (HVDC) CARBON CORE CONDUCTOR FOR USE IN TRANSMISSION LINES. THE PRODUCTION LINES WILL HAVE CAPACITY OF 8,000 MILES OF CONDUCTOR PER YEAR WITH PRODUCT THAT MEETS CUSTOMER SPECIFICATIONS.

CONDUCTIVE COMPOSITES NAN-MATERIALS SCALE-UP PROJECT ** FAADC MIGRATION NOTE - ACTION TYPE:"1" TO "A", ASSISTANCE TYPE:"5" TO "05", RECORD TYPE:"2", BUSINESS FUNDS INDICATOR:"NON", INDIVIDUAL RECIPIENT INDICATOR:"NO", RESEARCH AND DEVELOPMENT FUNDS INDICATOR:"YES", COMPETED OPPORTUNITY:"1" TO "C", NUMBER OF PROPOSALS OR APPLICATIONS:"1", AWARDING SUB-TIER AGENCY CODE "5700" DERIVED FROM AWARDING OFFICE CODE "FA8650", FUNDING SUB-TIER AGENCY CODE "5700" DERIVED FROM FUNDING OFFICE CODE "F4FBCN", PPOP COUNTRY CODE:"USA", SMALL BUSINESS INDICATOR:"O", SAM EXCEPTION:"X" **

GAN ON SIC RADAR/EW MMIC PRODUCTION CAPACITY; TAS #97X0360.

NIST CONSORTIUM/CONSORTIA FOR POST-COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) NANOELECTRONICS RESEARCH PROGRAM

NANOELECTRONIC COMPUTING RESEARCH (NCORE) PROPOSAL FOR NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY FUNDING OPPORTUNITY (2017-NIST-CSFC-01)

NIST CONSORTIUM FOR POST-COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) NANOELECTRONICS RESEARCH GRANT PROGRAM.

HIGH TEMPERATURE SUPERCONDUCTOR TRANSMISSION CABLE SYSTEM FOR INSTALLATION IN THE LONG ISLAND POWER GRID (LIPA 2)

DEFENSE PRODUCTION ACT (DPA) TITLE III - SUSTAINMENT AND ENHANCEMENT OF SPACE-QUALIFIED SOLAR CELL SUPPLY CHAIN

TAS: 970100: DPA TITLE III SPACE-QUALIFIED SOLAR CELL GERMANIUM SUBSTRATE SUPPLY CHAIN IMPROVEMENT PROJECT

COVID-19 DPA3 PROJECT ENTITLED, SPACE QUALIFIED SOLAR CELL SUPPLY CHAIN

RADIATION HARDENED CRYOGENIC READ OUT INTEGRATED CIRCUITS

DEVELOPMENT AND IN GRID DEMONSTRATION OF A TRANSMISSION VOLTAGE SUPERLIMITER TM FAULT CURRENT LIMITER

HIGH TEMPERATURE SUPERCONDUCTORS, INC. NEW SUPERCONDUCTORS AWARD CONTROL NUMBER: 2784-1734 TITLE: HIGH THROUGHPUT AND HIGH QUALITY, LOWER COST COATED CONDUCTORS HTSI WILL FOCUS ON INCREASING PRODUCTION SPEEDS OF HIGH-TEMPERATURE SUPERCONDUCTING COATED CONDUCTORS (CC) 5 TO 10 TIMES CURRENT LEVELS, WHILE AT THE SAME TIME REDUCING THEIR COST BY A FACTOR OF TEN. CC’S ARE MADE BY DEPOSITING SEVERAL LAYERS OF SPECIALTY OXIDE MATERIALS ON HASTELLOY METAL TAPES.

INTERDIGITATED BACK CONTACT SOLAR CELLS USING ION IMPLANTATION AND IN-SITU PATTERNING

TOPIC 1.4.3 WIDE BAND-GAP POWER DEVICES --- HIGH VOLTAGE SIC POWER DEVICES FOR ADVANCED POWER ELECTRONICS

RECOVERY ACT: FLOATING SILICON METHOD

TAS::89 0336::TAS RECOVERY GENESIC SEMICONDUCTOR INC WILL DEVELOP REVOLUTIONARY SEMICONDUCTOR TECHNOLOGY THAT WILL ALLOW EFFICIENT PROCESSING OF MEGA

CAMBRIDGE ELECTRONICS, INC. CONTROL#2166-1581 BASE AWARD SCALEUP PROJECT TITLE:8” 3DGAN FINFET TECHNOLOGY FOR ENERGY EFFICIENT DATA CENTERS AND 5G NETWORK'' CAMBRIDGE ELECTRONICS AIMS TO CREATE AN ECOSYSTEM AROUND THE 3DGAN TECHNOLOGY BY TRANSFERRING IT TO A US-BASED 8” SI FAB AND FORMING PARTNERSHIP WITH EPI-WAFER VENDORS, FOUNDRIES AND SEMICONDUCTOR CHIP AND MODULE MANUFACTURERS FOR COLLABORATIVE PRODUCT DEVELOPMENT.

SUSTAINABLE ECONOMIC MCHP STIRLING UNIT (SEMS)

COST REDUCTION FOR HIGH-EFFICIENCY ADVANCED POWER SIC MOSFETS (CHEAP SIC MOSFETS)

CONDUCT DESIGN WORK FOR BATTLE CREEK SALMON AND STEELHEAD RESTORATION

ADVANCED MANUFACTURING AND PERFORMANCE ENHANCEMENTS FOR REDUCED-COST SILICON CARBIDE MOSFETS

ENHANCED SECOND GENERATION (2G) HIGH TEMPERATURE SUPERCONDUCTING (HTS) WIRE FOR ELECTRIC MOTOR APPLICATIONS

SMART CORC® CABLE TERMINATIONS WITH INTEGRATED QUENCH DETECTION

AUTOMOTIVE-QUALIFIED 900 V/250 A SIC DMOSFETS WITH INTEGRATED SCHOTTKY RECTIFIERS

STABLE, LOW-LOSS JOINTS FOR HTS FUSION MAGNETS

TECHNICAL INNOVATIONS ENABLING A NEW DIRECT DRIVE WIND TURBINE GENERATOR

ENERGY-EFFICIENT RECONFIGURABLE UNIVERSAL ACCELERATOR INTERCONNECT

TAS::89 0222::TAS NEW PHASE I 2010 SBIR; TITLE: NEXT-GENERATION DETECTOR AND IMAGER DEVELOPMENT; PI: RICHARD HAYHURST

FREEZER

NEW TINA SBIR TOPIC Q CABLES AWARD TO ADVANCED CONDUCTOR TECHNOLOGIES LLC CONTROL NUMBER 1954 - 1689 PROJECT TITLE: ''LIGHTWEIGHT, HIGH-POWER DENSITY, SELF-PROTECTING SUPERCONDUCTING POWER CABLES AND CONNECTORS FOR ELECTRIC AIRCRAFT APPLICATIONS''

AFFORDABLE CRYOGEN-FREE POINT-OF-CARE 1.5 T EXTREMITY MRI

SBIR PHASE II: DISRUPTIVE SEMICONDUCTOR SOFTWARE TOOL FOR RECIPE OPTIMIZATION FOR DEPOSITION AND ETCHING PROCESSES

SBIR PHASE II: INTEGRATED VOLTAGE REGULATORS FOR SMALL FOOTPRINT, EFFICIENT POWER DELIVERY IN MOBILE ELECTRONICS

ADVANCED POWER CONVERSION SYSTEMS FEATURING SIC MOSFETS WITH IN-SITU RESTORATION CAPABILITIES

HIGH FIELD CORC SOLENOIDS

CMOS INTEGRATED WITH FLOAT ZONE PIXEL SENSOR

SUPERCONDUCTING WIRES FOR DIRECT WIND GENERATOR

HIGH RESOLUTION NEURO-MRI

CRYOGEN-FREE LIGHT-WEIGHT SUPERCONDUCTING BEAM BENDING MAGNETS FOR PROTON THERAPY

900 V/200 A SIC SCHOTTKY DIODE FABRICATION ON 150 MM SUBSTRATES IN A HIGH-VOLUME SI FOUNDRY FOR AUTOMOTIVE TRACTION INVERTERS

ALL-SILICON CARBIDE POWER MODULE BASED BOOST CONVERTER PLATFORM FOR GRID-TIED ENERGY STORAGE APPLICATIONS

A MULTI-GS/S, RADIATION TOLERANT ANALOG-TO-DIGITAL CONVERTER TO IMPROVE TIMING RESOLUTION AND ACCURACY OF PIXELATED DETECTORS

26/B: CORC® CABLE BASED HIGH FIELD HYBRID MAGNETS FOR FUTURE COLLIDERS

19/C: HIGH-TEMPERATURE SUPERCONDUCTING CABLES FOR COMPACT FUSION REACTORS

DEVELOPMENT OF CORC WIRES FOR USE IN CANTED COSINE THETA ACCELERATOR MAGNETS

REBCO COATED CONDUCTOR CABLES FOR FUSION MAGNETS

DEVELOPMENT OF DESIGNS, PROCESSES AND TECHNOLOGY FOR 200MM SILICON SENSORS

QUANTIFYING APPROPRIATE DE-RATING OF SIC MOSFETS SUBJECT TO COSMIC

REBCO COATED CONDUCTOR CABLES FOR ACCELERATOR MAGNETS

LONG TERM HIGH AMPACITY PERFORMANCE VALIDATION AND CONCEPT DEMONSTRATION OF ENCAPSULATED SMART COMPOSITE CONDUCTOR

SBIR PHASE II:NEXT GENERATION VERTICAL CAVITY SURFACE EMITTING LASERS

SBIR PHASE II: ROLL-TO-ROLL MANUFACTURING OF HIGHLY CRYSTALLINE THIN FILM SEMICONDUCTOR SUBSTRATES FOR FLEXIBLE ELECTRONICS

SBIR PHASE II: LOW-COST PACKAGING SOLUTION FOR SPACE-GRADE AND HIGH-RELIABILITY INTEGRATED CIRCUITS -THIS SMALL BUSINESS INNOVATION RESEARCH (SBIR) PHASE II PROJECT ENABLES THE USE OF MODERN PACKAGING TECHNOLOGIES FOR INTEGRATED CIRCUITS IN SPACE APPLICATIONS. WHILE FAILURES IN SATELLITES ARE COMMON AND HIGH INSURANCE CLAIMS DUE TO SUCH FAILURES ARE FREQUENT, THE SPACE INDUSTRY CONTINUES TO USE INTEGRATED CIRCUITS (ICS) THAT ARE EITHER UNRELIABLE (NON-SPACE-GRADE) AND ARE PRONE TO FAILURE, OR SPACE-GRADE ICS WITH LARGE AND COSTLY PACKAGING AND COMPROMISED PERFORMANCE. THIS INNOVATION OFFERS A COST-EFFECTIVE AND REDUCED-SIZE SOLUTION FOR THE PACKAGING OF ICS THAT CAN OPERATE RELIABLY OVER THE EXTREME TEMPERATURE CYCLES EXPERIENCED IN SPACE APPLICATIONS. WAFER LEVEL CHIP SCALE PACKAGING (WLCSP) IS LIGHTER, SMALLER, AND HAS SUPERIOR ELECTRICAL AND THERMAL PERFORMANCE WHEN COMPARED TO TRADITIONAL LEADED PACKAGING SOLUTIONS. THESE ATTRIBUTES MAKE IT DESIRABLE TO THE SPACE INDUSTRY BY REDUCING SIZE AND WEIGHT, WHILE NOT COMPROMISING PERFORMANCE. AS THIS PACKAGING TECHNOLOGY IS LIMITED DUE TO ITS PERFORMANCE UNDER TEMPERATURE CYCLING, THIS PROJECT SEEKS TO ADDRESS THIS RELIABILITY PROBLEM BY USING EXISTING MANUFACTURING TECHNIQUES COUPLED WITH A NOVEL DESIGN CONCEPT. THIS SMALL BUSINESS INNOVATION RESEARCH (SBIR) PHASE II PROJECT AIMS TO REDESIGN SPECIFIC LAYERS WITHIN THE EXISTING WAFER LEVEL CHIP SCALE PACKAGING (WLCSP) TO IMPROVE RELIABILITY UNDER TEMPERATURE CYCLING. THE TEMPERATURE CYCLE RELIABILITY PROBLEM IN THE WLCSP IS CAUSED BY A THERMAL EXPANSION RATE MISMATCH OF SILICON DIE AND THE COPPER CIRCUIT BOARD. THIS PROJECT WILL REDESIGN THE REDISTRIBUTION LAYER WITHIN THE WLCSP TO COMPENSATE FOR THIS MISMATCH BY EFFECTIVELY MOVING THE INTERCONNECTS ON THE SILICON DIE IN ACCORDANCE WITH THE FASTER MOVING PRINTED CIRCUIT BOARD (PCB). THIS PROJECT WILL MAKE THE BENEFITS OF WLCSP ACCESSIBLE FOR THE ENTIRE SPACE COMMUNITY. THIS AWARD REFLECTS NSF'S STATUTORY MISSION AND HAS BEEN DEEMED WORTHY OF SUPPORT THROUGH EVALUATION USING THE FOUNDATION'S INTELLECTUAL MERIT AND BROADER IMPACTS REVIEW CRITERIA.- SUBAWARDS ARE PLANNED FOR THIS AWARD.

EMPOWER SEMICONDUCTOR, INC.: NEW CIRCUITS SBIR AWARD. CONTROL NUMBER: 1736-1515 TITLE: ''RESONANT VOLTAGE REGULATOR ARECHITECTURE ELIMINATES 30-50% ENERGY CONSUMPTION OF DIGITAL IC'S''

SBIR PHASE II: ULTRA-LOW POWER MICROCONTROLLER DESIGN

AGILE PHOTONIC DELAY CHIP MODULE

SUPERCONDUCTING GRADIENT COIL FOR TARGETED THERAPY BY MICRO-PARTICLE NAVIGATION

SBIR PHASE II: RADIATION-HARDENED INTEGRATED CIRCUITS USING STANDARD PROCESS FLOWS, AND ELECTRONIC DESIGN AUTOMATION TOOL IMPLEMENTATION

SILICON CARBID OPTICALLY GATE SOLID STATE POWER SWITCH

LARGE AREA SIC GTO THYRISTOR DEVELOPMENT WIDEBANDGAP HIGH VOLTAGE HIGH FREQUENCY SWITCHES

SBIR PHASE II: A NOVEL MEMORY HAVING BOTH VOLATILE AND NON-VOLATILE MODES FOR HIGH PERFORMANCE, LOW POWER APPLICATIONS

SBIR PHASE II: IN-MEMORY ARTIFICIAL NEURAL NETWORK

SIC SEMICONDUCTOR SWITCHES FOR KLYSTRON MODULATORS

SBIR PHASE II: NOVEL CAPACITOR-LESS DYNAMIC RANDOM ACCESS MEMORY TECHNOLOGY WITH ENERGY EFFICIENCY, MANUFACTURABILITY, AND SCALABILITY

EXTENDING THE OPERATING CAPABILITIES OF ULTRA HIGH VOLTAGE SIC DEVICES

SBIR PHASE II: BRIGHT AND TUNABLE UV LIGHT EMITTER FROM ZNMGO NANOCRYSTALLINE SYSTEM

SEMISYNBIO CONSORTIUM AND ROADMAP DEVELOPMENT

NOVEL GAN TRANSISTORS FOR HIGH POWER SWITCHING APPLICATIONS

ADVANCED NEXT GENERATION HIGH EFFICIENCY LIGHTWEIGHT WIND TURBINE GENERATOR

ADVANCED MANUFACTURING AND MATERIAL MEASUREMENTS SOFTWARE TOOL WEAVE? FOR THE ACCELERATION AND AUTOMATION OF SEM IMAGE ANALYSIS IN THE SEMICONDUCTOR INDUSTRY

SIC OPTICALLY GATED HIGH POWER SOLID STATE SWITCH

LARGE AREA SIC GTO THYRISTOR DEVELOPMENT

NEW SIGEC AVALANCHE PHOTO-DIODES INTEGRATED WITH CMOS

MULTIFAMILY HOUSING SERVICE COORDINATORS

STTR PHASE I: HARNESSING GALLIUM OXIDE FOR HIGH-EFFICIENCY POWER CONVERSION IN DATA CENTERS - EVALUATION OF GALLIUM OXIDE POWER DEVICES IN POWER CONVERTERS -THE BROADER IMPACT/COMMERCIAL IMPACTS OF THIS SMALL BUSINESS TECHNOLOGY TRANSFER (STTR) PHASE I PROJECT IS TO ADDRESS THE INEFFICIENCIES THAT EXIST WITHIN POWER ELECTRONICS. POWER ELECTRONICS IS THE USE OF COMPONENTS AND CIRCUITS TO MODIFY THE VOLTAGE TO MAKE IT USABLE. ELECTRICITY GOES THROUGH MANY POWER CONVERSION STEPS UNTIL CHARGING A COMPUTER WITH A CUMULATIVE EFFICIENCY OF <80%. BY USING NEW SEMICONDUCTOR MATERIALS, THESE POWER CONVERSION STEPS CAN BE MADE MORE EFFICIENT. BY MAKING POWER ELECTRONICS MORE EFFICIENT, SIGNIFICANT COST SAVINGS CAN BE REALIZED, MAKING A POSITIVE ECONOMIC AND ENVIRONMENTAL IMPACT. THE BENEFITS OF THIS TECHNOLOGY ARE MOST OBVIOUS WITHIN HIGH POWER OR HIGH-POWER DENSITY APPLICATIONS. ELECTRIC VEHICLE CHARGING INFRASTRUCTURE, SOLAR FARMS, AND INDUSTRIAL APPLICATIONS ARE COMMERCIAL USE CASES THAT WILL DIRECTLY BENEFIT IN ADDITION TO IMPORTANT DEFENSE APPLICATIONS FOR AEROSPACE AND WEAPON SYSTEMS. THIS SMALL BUSINESS TECHNOLOGY TRANSFER (STTR) PHASE I PROJECT WILL USE THE NEXT-GENERATION ULTRA-WIDE BANDGAP SEMICONDUCTOR GALLIUM OXIDE (GA2O3). WITH ITS LARGE BANDGAP AND THE AVAILABILITY OF HIGH-QUALITY NATIVE SUBSTRATES, GA2O3 CAN MEET EMERGING NEEDS THAT CURRENT MATERIALS CANNOT READILY ADDRESS. THROUGH THIS GRANT, THE PROJECT TEAM WILL ENHANCE THE PERFORMANCE OF SCALED-UP GA2O3 DEVICES BY REFINING THEIR DESIGN TO MINIMIZE LOSSES. THESE IMPROVED DEVICES WILL BE TESTED IN INDUSTRY-RELEVANT CIRCUITS, ALLOWING THE TEAM TO QUANTIFY THEIR ECONOMIC AND TECHNICAL ADVANTAGES. SUCH CIRCUIT-LEVEL DATA WILL BE INSTRUMENTAL IN IDENTIFYING THE OPTIMAL OPERATING CONDITIONS (E.G., VOLTAGE, POWER, FREQUENCY) FOR GA2O3-BASED DEVICES AND IN GUIDING FURTHER ENGINEERING EFFORTS. THIS AWARD REFLECTS NSF'S STATUTORY MISSION AND HAS BEEN DEEMED WORTHY OF SUPPORT THROUGH EVALUATION USING THE FOUNDATION'S INTELLECTUAL MERIT AND BROADER IMPACTS REVIEW CRITERIA.- SUBAWARDS ARE PLANNED FOR THIS AWARD.

SBIR PHASE I: DEVELOPMENT OF A SILICON CONDUCTIVITY-CONTROLLED POWER TRANSISTOR -THE BROADER IMPACT/COMMERCIAL IMPACTS OF THIS SMALL BUSINESS INNOVATION RESEARCH (SBIR) PHASE I PROJECT ARE IN THE DEVELOPMENT OF A SEMICONDUCTOR DEVICE FOR USE IN POWER SYSTEMS. THE DEVICE, CALLED A SWITCH, WILL HAVE SIGNIFICANTLY LOWER POWER LOSSES THAN EXISTING SYSTEMS. IT HAS THE POTENTIAL TO TRANSFORM A WIDE RANGE OF POWER CONVERSION SYSTEMS. BY REDUCING ENERGY LOSSES, THIS TECHNOLOGY WILL DIRECTLY LEAD TO SIGNIFICANT SAVINGS. COMMERCIALLY MANUFACTURING THE PROPOSED SEMICONDUCTOR DEVICE IN THE US IS IMPORTANT TO MAINTAINING US COMPETITIVENESS AND CREATING JOBS IN THE CHIPS MANUFACTURING AREAS. THE GLOBAL HIGH VOLTAGE POWER SEMICONDUCTOR MARKET WAS VALUED AT USD 4.1 BILLION IN 2020 AND IS PROJECTED TO REACH USD 5.9 BILLION BY 2025. THIS SMALL BUSINESS INNOVATION RESEARCH (SBIR) PHASE I PROJECT AIMS TO COMMERCIALIZE AN INNOVATIVE AND PATENT-PENDING SILICON CONDUCTIVITY-CONTROLLED BIPOLAR TRANSISTOR (CCBT) TECHNOLOGY. THIS TECHNOLOGY IS DESIGNED TO SIGNIFICANTLY REDUCE BOTH CONDUCTION AND SWITCHING LOSSES IN HIGH-POWER ELECTRONICS, ADDRESSING A CRITICAL NEED IN THE INDUSTRY FOR MORE EFFICIENT AND COST-EFFECTIVE SOLUTIONS. THE SBIR PROJECT WILL DESIGN AND COMMERCIALIZE THE 4.5KV-CLASS SI-CCBT. PRELIMINARY SIMULATIONS DEMONSTRATE AN 80% REDUCTION IN CONDUCTION LOSS, A 70% REDUCTION IN SWITCHING LOSS, AND A 75% COST REDUCTION COMPARED TO CURRENT INSULATED GATE BIPOLAR TRANSISTOR (IGBT) AND INTEGRATED GATE-COMMUTATED THYRISTOR (IGCT) SOLUTIONS. THESE ADVANCEMENTS ARE EXPECTED TO HAVE A TRANSFORMATIVE IMPACT ON HIGH-POWER ELECTRONICS APPLICATIONS, INCLUDING SOLAR AND BATTERY STORAGE SYSTEMS, MEDIUM VOLTAGE MOTOR DRIVES, HVDC CONVERTERS, SOLID-STATE CIRCUIT BREAKERS, SOLID-STATE TRANSFORMERS, AND PULSE POWER SYSTEMS. THIS AWARD REFLECTS NSF'S STATUTORY MISSION AND HAS BEEN DEEMED WORTHY OF SUPPORT THROUGH EVALUATION USING THE FOUNDATION'S INTELLECTUAL MERIT AND BROADER IMPACTS REVIEW CRITERIA.- SUBAWARDS ARE NOT PLANNED FOR THIS AWARD.

TITLE: MICROELECTRONIC AND ADVANCED PACKAGING TECHNOLOGY (MAPT) ROADMAP DEVELOPMENT PURPOSE STATEMENT: THE PROJECT WILL ACCELERATE U.S. LEADERSHIP IN SEMICONDUCTORS BY ROADMAPPING NEEDS ACROSS THE FULL VALUE CHAIN FOR ADVANCED PACKAGING TECHNOLOGIES AND WORKFORCE DEVELOPMENT TO SUPPORT EMERGING MICROELECTRONICS APPLICATIONS. ACTIVITIES TO BE PERFORMED: THE PROJECT TEAM WILL FORM A CONSORTIUM TO IDENTIFY EMERGING APPLICATIONS AT THE CONVERGENCE OF SEMICONDUCTORS AND MICROELECTRONICS AND ASSOCIATED ADVANCED PACKAGING TECHNOLOGY NEEDS. THE PROPOSERS WILL CREATE A ROADMAP EXECUTIVE COMMITTEE TO COORDINATE THE ACTIVITIES OF APPLICATION WORKING GROUPS AND TECHNICAL WORKING GROUPS WHO WILL DEVELOP THE CONTENT FOR THE ROADMAP THROUGH PRIMARILY VIRTUAL CONFERENCING. THE CONSORTIUM WILL HOLD AN IN-PERSON 1.5-DAY CONFERENCE AT THE END OF THE FIRST YEAR OF ACTIVITIES TO ENSURE THE BROADER STAKEHOLDER COMMUNITY WILL HAVE SUFFICIENT INPUT INTO THE FINAL PUBLISHED ROADMAP. EXPECTED OUTCOMES: THE PROJECT DELIVERABLE WILL BE A CLEAR, ACTIONABLE AND WIDELY DISSEMINATED ROADMAP TO GUIDE TECHNOLOGY AND WORKFORCE DEVELOPMENT INVESTMENTS IN SEMICONDUCTOR ADVANCED PACKAGING TO SUPPORT U.S. COMPETITIVENESS. THE PROPOSERS ANTICIPATE THAT THE CONSORTIUM CONVENED WILL FOSTER PARTNERSHIPS ACROSS A DIVERSITY OF ORGANIZATIONS AND GEOGRAPHIES THAT WILL STIMULATE THE GROWTH OF THE U.S. ADVANCED PACKAGING ECOSYSTEM ACROSS THE SUPPLY CHAIN. INTENDED BENEFICIARIES: INTENDED BENEFICIARIES OF THE PROJECT OUTCOMES ARE THE DOMESTIC STAKEHOLDERS IN THE SEMICONDUCTOR ADVANCED PACKAGING AND MICROELECTRONICS INDUSTRY SECTORS. SUBRECIPIENT ACTIVITIES: THE RECIPIENT PLANS TO SUBAWARD FUNDS TO SUPPORT THE CONTRACTS FOR TARGETED TECHNOLOGY ASSESSMENTS AND MEETING SUPPORT.

MGB2 THIN FILM RIBBON CABLES

SBIR PHASE I: UNIVERSAL CRYSTAL GROWTH CAPSULE AND NOVEL WAFER DICING TOOL FOR IN-SPACE MANUFACTURING -THE BROADER IMPACT AND COMMERCIAL POTENTIAL OF THIS SMALL BUSINESS INNOVATION RESEARCH (SBIR) PROJECT IS IN ADVANCED SEMICONDUCTOR TECHNOLOGIES THAT ARE OF CRITICAL NEED FOR EMERGING AUTONOMOUS SYSTEMS, NETWORKED SENSING TECHNOLOGIES, ARTIFICIAL INTELLIGENCE ENABLED SYSTEMS, AEROSPACE, AND DEFENSE SURVEILLANCE SYSTEMS. IN-SPACE MANUFACTURING UNDER MICROGRAVITY CONDITIONS ENABLE UNIQUE MATERIALS CHARACTERISTICS AND ADVANCED SEMICONDUCTOR DEVICE DESIGNS WITH SIGNIFICANTLY HIGHER PERFORMANCES, THUS PROVIDING THE MOST APPROPRIATE PLATFORM FOR MEETING THE TECHNOLOGICAL AND MARKET DEMANDS. A NOVEL CLASS OF SEMICONDUCTOR BASED COMPOSITE MATERIALS WITH UNIQUE CHARACTERISTICS FOR NUMEROUS LARGE SCALE EMERGING APPLICATIONS INCLUDING, MAGNETIC SENSING, THERMOELECTRICS, PHOTOVOLTAIC POWER GENERATION, QUANTUM COMPUTING DEVICES, ETC. WILL BE DEVELOPED. THE PROPOSED MANUFACTURING PLANS WILL BENEFIT THE US NATIONAL DEFENSE AND CIVILIAN INDUSTRY. THE IN-SPACE MANUFACTURING PLATFORM WILL BOOST THE YIELD AND RELIABILITY FOR HIGH PERFORMANCE DEVICE TECHNOLOGIES, MEETING THE DEMAND OF THE MULTI-BILLION US$ MARKET. LESSONS LEARNT FROM THIS PROJECT WILL ACCELERATE THE SPACE MATERIALS PRODUCTION WITH POTENTIALLY HIGHER PROFIT MARGINS FOR SOLD GOODS AND ATTRACT PRIVATE SECTOR INVESTMENTS IN SPACE MANUFACTURING BUSINESS. THIS WILL HELP THE US DOMESTIC INDUSTRY TO GAIN AND/OR MAINTAIN LEADERSHIP IN MANY CRITICAL TECHNOLOGY SECTORS. THERE IS A NEED FOR HIGHER THROUGHPUT, HIGHER ITERATION IN-SPACE R&D AND MANUFACTURING TO DRIVE TO MEANINGFUL ADVANTAGES, AND THIS PROJECT WILL ENABLE AN ACCELERATION OF SUCH TRANSLATIONAL R&D IN SEMICONDUCTORS AND OTHER KEY SECTORS. ADDITIONALLY, WORKFORCE DEVELOPMENT (WFD) FOR TRAINING ENGINEERS AND TECHNICIANS IN SPACE BASED MANUFACTURING ARE IN PERFECT ALIGNMENT WITH THE PRIORITIES OF THE ?CHIPS FOR AMERICA? WORKFORCE DEVELOPMENT PLANS. THIS SBIR PHASE I PROJECT PROPOSES TO CREATE INNOVATIVE COMPONENT DESIGN AND MANUFACTURING APPROACHES FOR DEVELOPING TWO CRITICAL HARDWARE NECESSARY FOR IN-SPACE MANUFACTURING AND APPLICATION OF HIGH PURITY SEMICONDUCTOR GRADE BULK CRYSTALS. A UNIVERSAL CRYSTAL GROWTH CAPSULE DESIGN WILL BE DESIGNED AND FABRICATED FOR LEVERAGING MICROGRAVITY CONDITIONS DURING CRYSTAL GROWTH AND PROVIDING HIGH THROUGHPUT OF SPACE GROWN MATERIALS. FOR PROCESSING HIGH COST, LOW DEFECT CONTENT PREMIUM SPACE GROWN CRYSTALS, A NOVEL WAFER DICING TOOL FOR DAMAGE-FREE THIN FILM FABRICATION DIRECTLY FROM INGOTS WILL BE DEVELOPED. THE UNIVERSAL CAPSULE DESIGN WILL INCORPORATE ADVANCED HIGH TEMPERATURE FLUID DYNAMICS COMPONENTS THAT ARE NECESSARY FOR MAXIMIZING THE BENEFICIAL EFFECTS OF MICROGRAVITY ON CRYSTAL GROWTH. THE INNOVATIVE WAFER DICING TOOL ARCHITECTURE LEVERAGES ADVANCED OPTICS FABRICATION TECHNOLOGIES FOR CREATING THE DICING TOOL. THE PHASE 1 PROJECT WILL DEMONSTRATE CRYSTAL GROWTH OF SINGLE-PHASE ALLOY AND MULTI-PHASE COMPOSITES OF SEMICONDUCTOR-BASED MATERIALS. FABRICATION OF MICRON-SCALE THICK WAFERS WITH MILLIMETER SCALE CROSS-SECTION FOR DISCRETE SEMICONDUCTOR DEVICE FROM BULK CRYSTALS WILL BE DEMONSTRATED. THIS AWARD REFLECTS NSF'S STATUTORY MISSION AND HAS BEEN DEEMED WORTHY OF SUPPORT THROUGH EVALUATION USING THE FOUNDATION'S INTELLECTUAL MERIT AND BROADER IMPACTS REVIEW CRITERIA.- SUBAWARDS ARE NOT PLANNED FOR THIS AWARD.

SBIR PHASE I: ULTRA-LOW LOSS BEAMFORMER AND COMBINER-FIRST TECHNOLOGY FOR LOWER POWER, CONSUMPTION PHASED ARRAYS -THIS SMALL BUSINESS INNOVATION RESEARCH (SBIR) PHASE I PROJECT IS TO DEVELOP A NEW PHASED ARRAY COMMUNICATION TECHNOLOGY WHICH WILL BE ABLE TO ACHIEVE LOWER POWER CONSUMPTION, SMALLER FORM FACTORS, AND MORE AFFORDABLE PRICE TARGETS. PHASED ARRAYS ANTENNAS ARE ESSENTIAL FOR SATELLITE COMMUNICATIONS AND THE BROADER 5G, DEFENSE, AND AUTOMOTIVE RADAR MARKETS. THE COMPANY?S NEW PHASED ARRAY ARCHITECTURE WILL SIGNIFICANTLY DECREASE THE POWER CONSUMPTION AND THE NUMBER OF SILICON CHIPSETS THAT ARE REQUIRED. THIS IS PARTICULARLY IMPORTANT IN THERMALLY LIMITED AND POWER-CONSTRAINED ENVIRONMENTS LIKE MOBILE PLATFORMS AND SATELLITE COMMUNICATION SYSTEMS AND LEADS TO THE REDUCTION OF BATTERIES, BULKY POWER SUPPLIES, AND ADDITIONAL COOLING COMPONENTS. ADDRESSING THE HIGH COST AND POWER CONSUMPTION OF THESE PHASED ARRAYS WILL HAVE A SIGNIFICANT, POSITIVE IMPACT ON THE COMMERCIAL OPPORTUNITY BY ENABLING STEP CHANGES IN PERFORMANCE (LIKE DATA RATES AND CAPACITY) OR REDUCING COSTS FOR SENSITIVE CUSTOMER SEGMENTS. THIS SMALL BUSINESS INNOVATION RESEARCH PHASE I PROJECT WILL DEMONSTRATE A MORE POWER-EFFICIENT AND COST-EFFECTIVE PHASED ARRAY SEMICONDUCTOR TECHNOLOGY. THIS TECHNOLOGY USES A NOVEL ULTRA-LOW LOSS, HIGH-LINEARITY, PASSIVE BEAMFORMING CIRCUIT IN A UNIQUE LOW-POWER ARCHITECTURE. IN THE RECEIVE CONFIGURATION, THIS TECHNOLOGY WILL BE ABLE TO ACHIEVE A 75% REDUCTION IN POWER CONSUMPTION DUE TO A 4X REDUCTION IN THE NUMBER OF RECEIVER SIGNAL CHAINS. IN PHASE I, THE COMPANY AIMS TO ADVANCE THEIR ULTRA-LOW LOSS BEAMFORMING TECHNOLOGY TO ACHIEVE EVEN LOWER LOSSES, WHICH WILL ENABLE THE COMBINATION OF THE BEAMFORMER WITH THEIR UNIQUE LOW-POWER ARCHITECTURE. THE FOLLOWING OBJECTIVES REALIZE THESE GOALS: 1) DEVELOPMENT OF THE NOVEL ULTRA-LOW LOSS BEAMFORMER AND INTEGRATION WITH A RECEIVE FRONT-END, 2) FABRICATION AND PERFORMANCE OF BENCHTOP TESTING ON THE INTEGRATED RECEIVE CIRCUIT, AND 3) PERFORMANCE OF OVER-THE-AIR TESTING OF SMALL AND MODERATELY SIZED PHASED ARRAYS USING THE RECEIVE CIRCUIT. THE LOW-POWER BEAMFORMING TECHNOLOGY WILL OVERHAUL CURRENT PHASED ARRAYS, ELIMINATING MANY OF THE LOSSY, POWER-INTENSIVE AND EXPENSIVE COMPONENTS TRADITIONAL UNITS REQUIRE. THIS TECHNOLOGY WILL ENABLE THE CREATION OF HIGHER PERFORMANCE, LOWER COST PHASED ARRAYS FOR MANY CRITICAL INDUSTRIES RANGING FROM SATELLITE COMMUNICATION TO 5G TO RADAR. THIS AWARD REFLECTS NSF'S STATUTORY MISSION AND HAS BEEN DEEMED WORTHY OF SUPPORT THROUGH EVALUATION USING THE FOUNDATION'S INTELLECTUAL MERIT AND BROADER IMPACTS REVIEW CRITERIA.- SUBAWARDS ARE NOT PLANNED FOR THIS AWARD.

STTR PHASE I: NEXT-GEN RADIOFREQUENCY TRANSISTORS ON SILICON VIA ALIGNED, RESIDUE-FREE CARBON NANOTUBES -THE BROADER/COMMERCIAL IMPACT OF THIS SMALL BUSINESS TECHNOLOGY TRANSFER (STTR) PHASE I PROJECT SEEKS TO OVERCOME THE HIGHEST RISKS FACING THE COMMERCIALIZATION OF A NOVEL SEMICONDUCTOR FOR WIRELESS COMMUNICATIONS DEVICES. AS THE DEMAND FOR WIRELESS COMMUNICATION INCREASES (E.G., CELL PHONES, WIFI, INTERNET OF THINGS DEVICES), WIRELESS COMPONENT SUPPLIERS AND MANUFACTURERS MUST UTILIZE NEW MATERIALS AND INTEGRATION METHODS TO YIELD NECESSARY INCREASES IN DATA BANDWIDTH, ENERGY EFFICIENCY, AND FUNCTIONALITY, WHILE SHRINKING COMPONENT FOOTPRINT. CARBON NANOTUBES OFFER A SOLUTION TO THIS PROBLEM. A CARBON NANOTUBE IS COMPRISED OF AN ATOMICALLY THIN LAYER OF CARBON ROLLED INTO A SEAMLESS TUBE. CARBON NANOTUBES ACT LIKE TINY SEMICONDUCTING WIRES THAT CAN SIGNIFICANTLY OUTPERFORM CURRENT SEMICONDUCTORS SUCH AS SILICON AND GALLIUM ARSENIDE. WHEN ALIGNED INTO DENSE ARRAYS, NANOTUBES OFFER SUPERIOR WIRELESS CHARACTERISTICS INCLUDING HIGH FREQUENCY AND LINEARITY, WHICH ARE VITAL FOR NEXT-GEN COMMUNICATION TECHNOLOGIES. IMPORTANTLY, CARBON NANOTUBES CAN BE DEPOSITED ONTO EXISTING SEMICONDUCTORS (SUCH AS SILICON), ENABLING THE PREVIOUSLY UNFEASIBLE INTEGRATION OF MULTIPLE TYPES OF HIGH-PERFORMANCE CIRCUITS ON THE SAME CHIP, ALLOWING FOR MORE FUNCTIONALITY IN LESS SPACE. BY ADDRESSING PROBLEMS RELATED TO WIRELESS COMMUNICATION, THIS PROJECT WILL HAVE WIDESPREAD SOCIETAL IMPACT AND UNDERPIN THE WIRELESS RADIOFREQUENCY TECHNOLOGIES OF TOMORROW, WHILE BOLSTERING AMERICAN COMPETITIVENESS IN THIS IMPORTANT SECTOR. THE PROJECT WILL LEVERAGE RECENTLY DEVELOPED CARBON NANOTUBE ALIGNMENT TECHNOLOGY THAT OVERCOMES THE MATERIALS AND MANUFACTURING CHALLENGES THAT HAVE LIMITED PREVIOUS NANOTUBE RESEARCH AND DEVELOPMENT. THE ROOM-TEMPERATURE ALIGNMENT TECHNOLOGY IS FAST, COST-EFFECTIVE, AND AREA-SCALABLE ? ENABLING SEAMLESS INDUSTRY INTEGRATION. THE TECHNICAL INNOVATIONS OF THIS PROJECT WILL BE TO: (1) DEVELOP APPROACHES TO REMOVE ORGANIC PROCESSING RESIDUES THAT COAT THE SURFACES AND INTERFACES OF NANOTUBE ARRAYS AND DECREASE THE PERFORMANCE OF NANOTUBE-BASED WIRELESS COMMUNICATIONS TRANSISTORS; AND (2) FABRICATE AND DEMONSTRATE WIRELESS COMMUNICATIONS TRANSISTORS BASED ON ALIGNED NANOTUBES THAT DO NOT SUFFER FROM THE EFFECTS OF SUCH IMPURITIES. SPECTROSCOPIC MEASUREMENTS OF RESIDUES, ELECTRICAL MEASUREMENTS SENSITIVE TO IMPURITIES, AND ADDITIONAL HIGH FREQUENCY TRANSISTOR CHARACTERIZATION WILL BE USED IN A FEEDBACK LOOP TO INFORM RESIDUE REMOVAL PROCESS DEVELOPMENT. SPECIFIC ACTIVITIES WILL FOCUS ON: (1) SYSTEMATICALLY STUDYING THE EFFECT OF DIFFERENT TREATMENTS TO SELECTIVELY REMOVE RESIDUES; (2) DETERMINING HOW THE TREATMENTS DEPEND ON ARRAY DENSITY; AND (3) FABRICATING AND TESTING WIRELESS COMMUNICATIONS TRANSISTORS. THE PROJECT WILL PROVIDE A DATABASE OF IMPURITY REMOVAL RATES FOR A LIBRARY OF TREATMENTS, A DEMONSTRATION OF TRANSISTORS FREE OF PERFORMANCE LOSS FROM RESIDUES; AND A DEMONSTRATION OF NANOTUBE-BASED TRANSISTORS INTEGRATED ON SILICON. THIS AWARD REFLECTS NSF'S STATUTORY MISSION AND HAS BEEN DEEMED WORTHY OF SUPPORT THROUGH EVALUATION USING THE FOUNDATION'S INTELLECTUAL MERIT AND BROADER IMPACTS REVIEW CRITERIA.- SUBAWARDS ARE PLANNED FOR THIS AWARD.

SBIR PHASE I: MANUFACTURING OF GALLIUM NITRIDE (GAN) MEMBRANES FOR EFFICIENT THERMAL MANAGEMENT -THE BROADER IMPACT OF THIS SMALL BUSINESS INNOVATION RESEARCH (SBIR) PHASE I SEEKS TO PROVIDE GALLIUM NITRIDE (GAN) MEMBRANES FOR THE PRODUCTION OF SEMICONDUCTORS FOR NUMEROUS APPLICATIONS INCLUDING POWER ELECTRONICS, RADIO FREQUENCY DEVICES, AND OPTOELECTRONICS, ETC. THE PROOPOSED TECHNOLOGY SEEKS TO ALLEVIATE TWO MAJOR PROBLEMS IN THE CURRENT GAN-BASED MANUFACTURING TECHNOLOGY: THERMAL MANAGEMENT AND EXPENSIVE WAFER MATERIAL COSTS - BY PEELING OFF THE GAN MEMBRANE FROM THE PARENT WAFER AND INTEGRATING IT ON THE HEAT SINK. INTEGRATION OF THIN-FILM GAN ON A HEAT-SINK SUBSTRATE MAY SOLVE THE INTRINSIC THERMAL MANAGEMENT ISSUES OF GAN-BASED DEVICES BY EFFICIENTLY DISSIPATING THE HEAT. COMMERCIALIZATION OF PROPOSED TECHNOLOGY COULD DECREASE PRODUCTION COSTS OF GAN-BASED DEVICES BY REUSING THE EXPENSIVE PARENT SUBSTRATE MULTIPLE TIMES WHILE MAINTAIN THE MATERIAL QUALITY. GALLIUM NITRIDE-BASED TECHNOLOGIES HAVE BEEN WIDELY ADAPTED IN VARIOUS FIELDS INCLUDING HEALTHCARE AND DEFENSE, 5G NETWORKS, CLEAN ENERGY APPLICATIONS, ELECTRICAL VEHICLES, POWER INVERTERS AND MOBILE DEVICE CHARGERS, ETC. THIS PROJECT PROPOSES TO MANUFACTURE THE HIGH-QUALITY, FREE-STANDING GAN MEMBRANES INTEGRATED ON HEAT SINKS BY USING TWO UNIQUE TECHNOLOGIES: REMOTE EPITAXY AND 2-DIMENSIONAL LAYER TRANSFER (2DLT). REMOTE EPITAXY AND 2DLT TECHNOLOGIES UTILIZE 2D MATERIALS INSERTED BETWEEN THE SUBSTRATE AND EPILAYER FOR THE GROWTH AND LIFT-OFF OF GAN THIN-FILM. COMBINATION OF REMOTE EPITAXY AND 2DLT PROCESSES ALLOW FOR THE PRODUCTION OF HIGH-QUALITY GAN MEMBRANES WITH MULTIPLE REUSES OF COSTLY GAN SUBSTRATES. FEASIBILITY OF PROPOSED TECHNOLOGY WILL BE CONFIRMED VIA TIME-DOMAIN THERMOREFLECTANCE (TDTR) TECHNIQUES BY MEASURING THE GAN AND HEAT SINK INTERFACE. THIS AWARD REFLECTS NSF'S STATUTORY MISSION AND HAS BEEN DEEMED WORTHY OF SUPPORT THROUGH EVALUATION USING THE FOUNDATION'S INTELLECTUAL MERIT AND BROADER IMPACTS REVIEW CRITERIA.

STTR PHASE I: LOW-COST PACKAGING SOLUTION FOR SPACE-GRADE AND HIGH-RELIABILITY INTEGRATED CIRCUITS

REDUCING THE SIZE AND COST OF MRI BY USING A ZERO-HE MODERATE-FIELD MRI MAGNET INTEGRATED WITH A CRYOCOOLED RF COIL

SBIR PHASE I: ULTRA POWER-EFFICIENT ANALOG AND BIO-INSPIRED INTEGRATED CIRCUITS FOR WEARABLE COMPUTING

SBIR PHASE I: SWITCHING-FREE DC VOLTAGE CONVERSION

SBIR PHASE I: ULTRA-HIGH SPEED IN-MEMORY SEARCHABLE DYNAMIC RANDOM ACCESS MEMORY

STTR PHASE I: HIGH-RELIABILITY SIC POWER MOSFETS FOR ENERGY EFFICIENT POWER ELECTRONICS INFRASTRUCTURE

SBIR PHASE I: ROLL-TO-ROLL MANUFACTURING OF HIGHLY CRYSTALLINE THIN FILM SEMICONDUCTOR SUBSTRATES FOR FLEXIBLE ELECTRONICS

SBIR PHASE I: FABRICATION OF VERTICAL JUNCTION GAN FET DEVICES VIA PULSED LASER ANNEALING PROCESS

SBIR PHASE I: DISRUPTIVE SEMICONDUCTOR SOFTWARE TOOL FOR RECIPE OPTIMIZATION FOR DEPOSITION AND ETCHING PROCESSES

HIGH PERFORMANCE COMPUTING FOR RAPID DESIGN AND OPTIMIZATION OF ROLL-TO-ROLL ETCH PROCESSES

AUTOMOTIVE-QUALIFIED 3300 V SIC MOSFETS FOR NEXT-GENERATION EXTREME FAST CHARGERS

CORC CABLES WOUND FROM OVERLAPPING TAPES

DEVELOPMENT OF LONG-LENGTH CORC CABLES AND CABLE-IN-CONDUIT-CONDUCTORS FOR COMPACT FUSION REACTORS

NEXT GENERATION HIGH-TEMPERATURE SUPERCONDUCTING CORC CONDUCTORS FOR HIGH-FIELD ACCELERATOR MAGNETS

HYBRID ACCELERATOR MAGNETS BASED ON DOG BONE SHAPED CORC; WIRE INSERTS FOR OPERATION BEYOND 20 T

MICRO-TRANSFER-PRINTING OF REPEATERS ON PASSIVE INTERPOSER

HIGH-STRENGTH COMPOSITE HTS CORC CABLES FOR PLASMA FUSION CONFINEMENT SYSTEMS

CANCELLATION - NEW SBIR PHASE I 2009: DEVELOPMENT OF AN ACCELERATED LIFE TEST FOR WIDE-BANDGAP (SIC) HEV/PHEV POWER CONVERSION MODULES; PI - RANBIR S

3D THICK WAFER ACTIVE PIXEL SENSOR

NOVEL REEL-TO-REEL REBCO CC QUALITY CONTROL SYSTEM FOR FUSION ELECTRICITY GENERATION APPLICATIONS

NON-INVASIVE DETECTION OF INTERFACIAL DEBONDING AND MECHANICAL FAILURES IN HIGH FIELD MAGNETS USING ULTRASONIC WAVE

SBIR PHASE I: INTEGRATED VOLTAGE REGULATORS FOR SMALL FOOTPRINT, EFFICIENT POWER DELIVERY IN MULTI-CORE SOCS

SBIR PHASE I: SINGLE-MODE SINGLE-POLARIZATION VCSELS AT ANY WAVELENGTH

SBIR PHASE I: NOVEL CAPACITOR-LESS DYNAMIC RANDOM ACCESS MEMORY TECHNOLOGY WITH ENERGY EFFICIENCY, MANUFACTURABILITY, AND SCALABILITY

SBIR PHASE I: SIGEC SUPERLATTICES WITH DIRECT BANDGAPS FOR LIGHT EMISSION AND ABSORPTION AT 1.55 MICRONN

SBIR PHASE I: OPTIMIZATION OF A SINTERING AND MANUFACTURING PROCESS FOR PROTOTYPE MGB2 WIRES FOR NEXT-GENERATION CRYOGENIC-FREE 1.5T AND 3.0T MRI

SBIR PHASE I: ULTRA POWER-EFFICIENT BIOLOGICALLY-INSPIRED INTEGRATED CIRCUIT ARCHITECTURES FOR THE PROCESSING AND CLASSIFICATION OF ANALOG SENSOR SI

DEVELOPMENT OF REPORTING, MONITORING AND PERFORMANCE ASSESSMENT FOR ICOCA

TO REINFORCE THE COMMUNITY COALITIONS OF LIMA, CALLAO AND THE PROVINCES, SOLIDIFYING ALL THE SECTORS THAT COMPRISE THEM AND STRENGTHENING THEIR ORGAN

DIRECT INVERSION WIND POWER SYSTEM BASED ON FIELD BALANCED WBG TECHNOLOGY

SILICON CARBIDE QUASI-BIPOLAR JUNCTION TRANSISTOR (QBJT)-BASED BOOST CONVERTER PLATFORM FOR UP-TOWER WIND APPLICATIONS

1200 V/50 A ALGAN-GAN-SI MOS-HFETS AND SCHOTTKY RECTIFIERS

15 KV LEG MODULES WITH SIC MONOLITHICALLY INTEGRATED JBS RECTIFIER WITH SUPER JUNCTION TRANSISTOR (MIDSJT) DEVICES

SBIR PHASE I: ANALOG POWER SUPPLY INTEGRATED CIRCUIT SYSTEM FOR HIGH INTENSITY LIGHT EMITTING DIODE LIGHTING

SBIR PHASE I: RADIATION HARDENED INTEGRATED CIRCUITS FOR CT SCANNERS WITH REDUCED RADIATION EXPOSURE

SBIR PHASE I: NEXT GENERATION VERTICAL CAVITY SURFACE EMITTING LASERS

SBIR PHASE I: VCSELS ON SILICON: CMOS COMPATIBLE EPITAXIAL MESAS ON LARGE SILICON WAFERS

SBIR PHASE I: A NOVEL MEMORY HAVING BOTH VOLATILE AND NON-VOLATILE MODES FOR HIGH PERFORMANCE LOW POWER APPLICATIONS

SBIR PHASE I: FAST SLEWING VOLTAGE REGULATOR FOR PACKAGE INTEGRATED DYNAMIC VOLTAGE AND FREQUENCY SCALING APPLICATIONS

SBIR PHASE I: HIGH-PERFORMANCE ANALOG-TO-DIGITAL CONVERSION FOR BROADBAND APPLICATIONS

FLEX-3D WAFER PROCESSING FOR CHIP STACKING AND INTERCONNECT

DEVELOPMENT OF 600V, 100A SIC SCHOTTKY DIODES IN A 150MM SI FOUNDRY FOR ELECTRIC VEHICLE TRACTION INVERTER APPLICATIONS

COPPER NANO-TSVS FOR 3D INTEGRATED SENSORS

HIGH-CURRENT SIC MOSFETS FOR AUTOMOTIVE APPLICATIONS

HIGH-CURRENT DENSITY CORC® WIRES FOR USE IN ACCELERATOR MAGNETS

AN ACTIVE PIXEL SENSOR FABRICATED USING 5MM THICK SI WAFER MATERIAL

DEMOUNTABLE JOINTS FOR HTS FUSION CABLES

SMART CORC CABLES

DEVELOPMENT OF THE CAPACITIES REINFORCEMENT STAGES OF POLICY ACTIVATION AND MANAGEMENT TO CONSOLIDATE THE ORGANIZATIONAL SUSTAINABILTY AND GO AHEAD I

YBCO COATED CONDUCTOR WITH AN INTEGRATED OPTICAL FIBER SENSORS

DEVELOPMENT OF THE CAPACITIES REINFORCEMENT STAGES OF POLICY ACTIVATION AND MANAGEMENT TO CONSOLIDATE THE ORGANIZATIONAL SUSTAINABILITY AND GO AHEAD

"TO CONSOLIDATE EXPAND AND REPLICATE THE COMMUNITY ANTI-DRUG COALITION IN SANTIAGO DE SURCO AND CONSOLIDATE CONSORTIUM IN SAN JUAN DE MIRAFLORES" CR

DEVELOPMENT OF THE CAPACITIES REINFORCEMENT STAGES OF POLICY ACTIVATION AND MANAGEMENT TO CONSOLIDATE THE ORGANIZATIONAL SUSTAINABILITY AND GO AHEAD

SBIR PHASE I: BRIGHT AND TUNABLE UV LIGHT EMITTER FROM ZNMGO NANOCRYSTALLINE SYSTEM

HOCKEY PUCK NEUTRON DETECTOR DEMO

DEVELOPMENT OF THE CAPACITIES REINFORCEMENT STAGES OF POLICY ACTIVATION AND MANAGEMENT TO CONSOLIDATE THE ORGANIZATIONAL SUSTAINABILITY AND GO AHEAD

SBIR PHASE I: ION IMPLANTATION-FREE SIC DEVICE FABRICATION TECHNOLOGY BASED ON LOW-TEMPERATURE SELECTIVE EPITAXIAL GROWTH

ADVANCED MANUFACTURING AND MATERIAL MEASUREMENTS SOFTWARE TOOL WEAVE FOR THE ACCELERATION AND AUTOMATION OF SEM IMAGE ANALYSIS IN THE SEMICONDUCTOR INDUSTRY

SBIR PHASE I: A NOVEL SEMICONDUCTOR MEMORY HAVING BOTH VOLATILE AND NON-VOLATILE MODES

NEW CA - ULTRA-HIGH VOLTAGE SILICON CARBIDE SUPER CASCODE SWITCHES

WORKSHOP FOR A FUTURE NANOTECHNOLOGY INFRASTRUCTURE SUPPORT PROGRAM, AUGUST 18-19, 2014, WESTIN ARLINGTON GATEWAY HOTEL, ARLINGTON, VA.

THE PURPOSE OF THIS ONE YEAR GRANT IS TO ASSIST CRESER IN THE CONSOLIDDATION, SUSTAINABILITY AND EXPANSION OF THE CAC LOCATES IN UCAYALI.

THE PURPOSE OF THIS ONE YEAR GRANT IS TO ASSIST CRESER IN THE CONSOLIDATION,SUSTAINABILITY AND EXPANSION OF THE CAC LOCATED IN HUANUCO.

COMMUNITY ANTI-DRUG COALITION (CAC) IN "UCAYALI."THE PURPOSE OF THIS ONE YEAR CA IS TO CREATE TWO CAC WITHIN THE PROVINCE OF CORONEL PORTILLO, IN T

ASSIST CRESER IN THE CONSOLIDATION SUSTAINABILITY AND EXPANSION OF THE CAC LOCATED IN SAN JUAN DE MIRAFLORES.

THE PURPOSE OF THIS ONE YEAR GRANT IS TO ASSIST CRESER IN THE CONSOLIDATION SUSTAINABILITY AND EXPANSIONOF CAC LOCATED IN COMAS.

THE PURPOSE OF THIS ONE YEAR GRANTS IS TO ASSIST CRESER IN THE CONSOLIDATION, SUSTAINABILITY AND EXPANSION OF THE CAC LOCATED IN LOS OLIVOS.

COMMUNITY ANTI-DRUG COALITION (CAC) IN "HUANUCO."THE PURPOSE OF THIS ONE YEAR CA IS TO CREATE TWO CAC WITHIN THE PROVINCE AND REGION HUANUCO. THIS P

VERIFICATION, VALIDATION, AND TEST OF ML SYSTEMS (V-TML) WORKSHOP

THE DEVELOPMENT OF A COLLABORATIVE RESEARCH PLAN FOR NIST AND THE SEMICONDUCTOR INDUSTRY FOR NANOELECTRONICS RESEARCH IN THE BIO-SCIENCES

WORKSHOP ON ENABLING A FUTURE INFORMATION TECHNOLOGY REVOLUTION, MARCH 30-31, 2015, IBM CONFERENCE CENTER, WASHINGTON, DC

WORKSHOP ON FAILURE AND UNCERTAINTY IN MIXED-SIGNAL CIRCUITS AND SYSTEMS JULY 8-9 2010 ARLINGTON VA

WORKSHOP ON INTELLIGENT COGNITIVE ASSISTANTS (ICA). TO BE HELD NOVEMBER 14-15, 2017 IN SAN JOSE, CALIFORNIA.

FORUM ON NANOELECTRONIC MANUFACTURING: FROM MATERIALS TO SYSTEMS

FORUM ON INTEGRATED SENSORS FOR CYBERSYSTEMS (FISC-2030)

WORKSHOP: SRC/NSF FORUM ON 2020 SEMICONDUCTOR MEMORY STRATEGIES: PROCESSES, DEVICES, AND ARCHITECTURES, SEPTEMBER, 2009.

WORKSHOP ON ENERGY EFFICIENT COMPUTING

ASSIST CRESER IN THE CONSOLIDATION, SUSTAINABILITY AND EXPANSION OF THE CAC LOCATED IN VILLA MARIA DEL TRIUNFO.

MULTIFAMILY HOUSING SERVICE COORDINATORS

AN ASSESSMENT OF OPTIONS FOR POST-CMOS EMERGING RESEARCH DEVICES AND RELATED MATERIALS: FOUR WORKSHOPS TO BE HELD IN 2012 IN THE NETHERLANDS, CANADA,

INTERNATIONAL MINI-WORKSHOP SERIES ON AN ASSESSMENT OF OPTIONS FOR POST-CMOS EMERGING RESEARCH DEVICES AND RELATED MATERIALS TO BE HELD APRIL - NOV.

INTERNATIONAL MINI-WORKSHOP SERIES ON "AN ASSESSMENT OF OPTIONS FOR POST-CMOS EMERGING RESEARCH DEVICES AND RELATED MATERIALS". TO BE HELD IN 2008 I

WORKSHOP ON SCENARIOS FOR BRAIN-INSPIRED COGNITIVE ASSISTANTS, SAN JOSE CA, MAY 12-13TH.

WORKSHOP ON MICROSYSTEMS FOR ELECTROCEUTICALS AND BIOELECTRONIC MEDICINE, APRIL 12-13, 2017, IBM CONFERENCE CENTER WASHINGTON DC.

SRC WORKSHOP ON BIOLOGICAL PATHWAYS FOR ELECTRONIC NANOFABRICATION AND MATERIALS

TO SUPPORT AN INTERNATIONAL CONDUCTORS CONFERENCE.

TO SUPPORT CONDUCTOR TRAINING WORKSHOPS.

TO SUPPORT CONDUCTOR TRAINING WORKSHOPS.

TAS::57 3600::TAS "THE EIGHTH INTERNATIONAL WORKSHOP ON FUTURE INFORMATION PROCESSING TECHNOLOGIES"

TO SUPPORT CONDUCTOR TRAINING EDUCATION WORKSHOPS.

TO SUPPORT CONDUCTOR TRAINING WORKSHOPS AT THE UNIVERSITY OF NORTH TEXAS IN DENTON AND WITH THE RICHMOND SYMPHONY, RICHMOND, VIRGINIA.

TO SUPPORT CONDUCTOR TRAINING WORKSHOPS.

MULTIFAMILY HOUSING SERVICE COORDINATORS

INTERNATIONAL LINEAR COLLIDER PIXEL ARRAY VERTEX DETECTOR DEVELOPMENT

LOW AC LOSS YBCO COATED CONDUCTOR GEOMETRY BY DIRECT INKJET PRINTING

SIC SEMICONDUCTOR SWITCHES FOR KLYSTRON MODULATORS

HTS TRANSMISSION CABLE SYSTEM FOR INSTALLATION IN THE LONG ISLAND POWER GRID (LIPA 2)

MAGNETIC COMMUNICATION NETWORK FOR SMART PHOTOVOLTAIC SOLAR POWER MODULES

DEVELOPMENT AND IN-GRID DEMONSTRATION OF A TRANSMISSION VOLTAGE SUPERLIMITERTM FAULT CURRENT LIMITER